Optimized VLSI Circuit Partitioning and Testing Using ACO and BIST Architectures

Circuit partitioning, an essential strategy in physical design, involves dividing a circuit according to specific constraints to meet particular objectives. These objectives frequently include minimizing the cut set between partitions, reducing the delay across partitions, maximizing partition sleep time to reduce power consumption, and assessing the algorithm’s time complexity. Previous efforts have introduced several improvement techniques to accomplish these goals. This study explores different optimization methods and introduces a hybrid algorithm, to further reduce area and power consumption while incorporating Built-In Self-Test architecture for effective circuit testing. Experimental evaluations were carried out using Xilinx Vivado and Microwind tools.